Semiconductor device having a passivation layer
US5763905A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 9, 1996 |
| Grant date | Jun 9, 1998 |
| Priority date | — |
| Expiry date | Jul 9, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D8/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device comprising at least one SiC semiconductor layer; and passivation layers applied on at least a portion of a surface of the SiC semiconductor layer for passivation thereof; the passivation layers comprising at least a substantially insulating layer comprising crystalline AlN and placed next to the SiC semiconductor layer and a semi-insulating layer allowing a weak current to flow therein in a blocking state of the device; wherein the semi-insulating layer comprises at least one first sub-layer and at least one second sub-layer, the at least one first sub-layer having a smaller gap between a conduction band and a valence band thereof than the at least one second sub-layer and the at least one second sub-layer having dopants for auto-ionization thereof by transport of charge carriers thereof to a deeper energy state in the semi-insulating sub-layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.