Semiconductor device including retrograde well structure with suppressed substrate bias effects
US5763921A · kind A · utility
131Cited by
4References
2Claims
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Key dates
| Filing date | May 14, 1996 |
| Grant date | Jun 9, 1998 |
| Priority date | — |
| Expiry date | May 14, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
An n well and a p well are formed in a silicon substrate. The n well has n type impurity concentration peaks and a p type impurity concentration peak. The p well has p type concentration peaks. The impurity concentration peaks serving as channel stopper regions for isolating elements exist only in proximity to the lower surface of an isolation oxide film but not in element regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.