Dynamic latching device

US5764089A · kind A · utility

Assignee

• Altera Corporation · US

Inventors

• Hamid Partovi · Sunnyvale, US
• Robert C. Burd · Santa Clara, US
• Udin Salim · San Jose, US
• Frederick Daniel Weber · San Jose, US
• Luigi Di Gregorio · Sunnyvale, US
• Donald A. Draper · San Jose, US

Key dates

• Filing date: Aug 30, 1996
• Grant date: Jun 9, 1998
• Expiry date: Aug 30, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K3/037
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A high-performance dynamic flip-flop circuit implementation. The dynamic flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (319). The flip-flop comprises a delay block (317) coupled to a clock input (305). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (440) of the delayed clock output (319) follows a rising edge (444) of a clock signal after a delay period (448). The flip-flop clocks in new data at a data input (305) in response to the clock input (310) during this delay period (448). Data is held in a storage block (360). The flip-flop has extremely good transient characteristics, especially set-up and clock-to-output times. The flip-flop consumes no static power.