Frederick Daniel Weber
80Patents
46h-index
48Co-inventors
88Inventor score
Filing activity: Dec 22, 1987 → Nov 22, 2016
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6105129A | Converting register data from a first format type to a second format type if a second type instruction consumes data produced by a first type instruction | Physics | 238 | Expired |
| US8397013B1 | Hybrid memory module | Electricity | 192 | Active |
| US7472220B2 | Interface circuit system and method for performing power management operations utilizing power management signals | Physics | 150 | Active |
| US7386656B2 | Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit | Physics | 139 | Active |
| US7590796B2 | System and method for power management in memory systems | Physics | 138 | Active |
| US7724589B2 | System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits | Physics | 137 | Active |
| US7761724B2 | Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit | Physics | 136 | Active |
| US7392338B2 | Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits | Physics | 135 | Active |
| US7581127B2 | Interface circuit system and method for performing power saving operations during a command-related latency | Physics | 134 | Active |
| US7609567B2 | System and method for simulating an aspect of a memory circuit | Physics | 133 | Active |
| US7730338B2 | Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits | Physics | 133 | Active |
| US7580312B2 | Power saving system and method for use with a plurality of memory circuits | Physics | 132 | Active |
| US8089795B2 | Memory module with memory stack and interface with enhanced capabilities | Electricity | 131 | Active |
| US5055999A | Multiprocessor digital data processing system | Physics | 129 | Expired |
| US6093213A | Flexible implementation of a system management mode (SMM) in a processor | Physics | 124 | Expired |
| US5297265A | Shared memory multiprocessor system and method of operation thereof | Physics | 90 | Expired |
| US6298438A | System and method for conditional moving an operand from a source register to destination register | Physics | 87 | Expired |
| US8244971B2 | Memory circuit system and method | Physics | 84 | Active |
| US8209479B2 | Memory circuit system and method | Emerging Cross-Sectional Technologies | 82 | Active |
| US5909572A | System and method for conditionally moving an operand from a source register to a destination register | Physics | 81 | Expired |
| US5764089A | Dynamic latching device | Electricity | 80 | Expired |
| US8019589B2 | Memory apparatus operable to perform a power-saving operation | Emerging Cross-Sectional Technologies | 78 | Active |
| US8667312B2 | Performing power management operations | Physics | 76 | Active |
| US8041881B2 | Memory device with emulated characteristics | Emerging Cross-Sectional Technologies | 74 | Active |
| US6173366A | Load and store instructions which perform unpacking and packing of data bits in separate vector and integer cache storage | Electricity | 74 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.