Semiconductor memory device
US5764562A · kind A · utility
46Cited by
3References
27Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 14, 1996 |
| Grant date | Jun 9, 1998 |
| Priority date | — |
| Expiry date | Feb 14, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4074
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell is connected between a bit line and an electrode node. The memory cell includes a transistor connected to the bit line and a capacitor connected to the electrode node. In the operation, the potential of a word line is raised after the potential of the electrode node is lowered to the L-level. Thereby, electric charges are read onto the bit line from only the memory cell connected to the electrode node of which potential is selectively lowered. Therefore, only the selected bit line among the plurality of bit lines can be operated. Consequently, the power consumption can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.