Method and apparatus for implementing a dual processing protocol between processors
US5764932A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1996 |
| Grant date | Jun 9, 1998 |
| Priority date | — |
| Expiry date | Dec 23, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To improve computer performance, a second processor can be added to a computer system. However, when a second processor is added to a computer system, a dual processing protocol is required to ensure that the two processors share the computer resources. A robust dual processing protocol is introduced that allows two processors to share a single processor bus in an efficient manner. The dual processing protocol allows pipelined bus transfers wherein partial control of the bus is transferred. Furthermore, the dual processing protocol ensures cache coherency by having any modified cache line written back to main memory when a memory location represent by a modified internal cache line is accessed. The dual processing Protocol is designed to support a well defined fair and robust arbitration DP protocol between two processors that is independent of the core frequency and the bus fraction ratio. As such, the dual processing protocol is functional even if the two processors are running with different bus fractions ("heterogeneous DP"). The dual processing protocol is a Pure Bus Clock based protocol such that all the indications on the private interface are in pure bus-clock domain. This …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.