Method for distributing interprocessor interrupt requests via cache memory coherency mechanisms
US5765195A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 8, 1995 |
| Grant date | Jun 9, 1998 |
| Priority date | — |
| Expiry date | Dec 8, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism for distributing interrupts to processors within a multi-processing system including a cache memory corresponding to each processor, a main memory, a bus structure connecting the processors and their associated cache memories with the main memory, and a cache coherency mechanism to maintain data consistency between the cache memories and the main memory. An address within the main memory is assigned to each processor within the system, the assigned address being associated with an interrupt for the processor to which it is assigned. For each processor, a copy of the contents of its assigned address is thereafter read into its corresponding cache memory. Thereafter when a cache coherency operation to update the contents or status of the cache memory address occurs, a comparison is made between the cache memory address presented to the cache memory through the system bus structure and a stored interrupt base address. An interrupt signal for the processor is generated when the comparison determines a match between the cache memory address presented to the cache memory through the system bus structure and a stored interrupt base address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.