CMOS process utilizing disposable silicon nitride spacers for making lightly doped drain
US5766991A · kind A · utility
39Cited by
20References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 29, 1996 |
| Grant date | Jun 16, 1998 |
| Priority date | — |
| Expiry date | Aug 29, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/859
Abstract
A process sequence for fabricating CMOS devices of the LDD type includes forming spacers along the sides of gates defined on p- and n-regions of the device. In a two-mask sequence, a thin layer of silicon dioxide is utilized to protect the n-region spacers while the p-region spacers are etched away. In one-mask variants of this sequence, a thin layer of silicon oxynitride is utilized to prevent oxide growth over one type of region while an oxide implant mask is grown on the surface of the other type of region and on exposed surfaces of the gates overlying the other type of region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.