SOI CMOS structure
US5767549A · kind A · utility
356Cited by
8References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 3, 1996 |
| Grant date | Jun 16, 1998 |
| Priority date | — |
| Expiry date | Jul 3, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
An integrated circuit is described incorporating a substrate, a layer of insulator, a layer of silicon having raised mesas and thin regions therebetween to provide ohmic conduction between mesas, electronic devices on the mesas, and interconnection wiring. The invention overcomes the problem of a floating gate due to charge accumulation below the channel of MOS FET's.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.