Semiconductor memory device
US5768195A · kind A · utility
59Cited by
5References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 16, 1997 |
| Grant date | Jun 16, 1998 |
| Priority date | — |
| Expiry date | May 16, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device according to he present invention comprises a first conductivity-type semiconductor substrate in which a second conductivity-type well is formed, a memory cell array composed of a plurality of memory cells arranged in a matrix in the second conductivity-type well, and a substrate voltage control circuit selectively outputting an output voltage to the substrate according to an external input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.