System and method for altering the clock frequency to a logic controller controlling a logic device running at a fixed frequency slower than a computer system running the logic device
US5768571A · kind A · utility
0Cited by
5References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 29, 1996 |
| Grant date | Jun 16, 1998 |
| Priority date | — |
| Expiry date | Aug 29, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for altering a clock frequency to a logic controlling device that controls logic which runs at a fixed frequency slower than a frequency of a computer system running the logic. The system speeds up the clock signal to a logic controller when the logic controller is arbitrating between different operational requests. When the logic controller acknowledges a specific operational request, the clock controller immediately slows the clock signal down in order to allow a command strobe length that the logic device executing a specific operation request requires.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.