Planarized capacitor array structure for high density memory applications
US5770499A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 1997 |
| Grant date | Jun 23, 1998 |
| Priority date | — |
| Expiry date | May 29, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/68
Abstract
A planarized capacitor array (182) and method of forming the same for high density applications. A storage node contact (116) is formed through an interlevel dielectric (110) on a semiconductor body (102). Then, an oxide layer (170) having a first thickness is deposited over the interlevel dielectric (110) and the storage node contact (116). A nitride layer (172) having a second thickness is deposited over the oxide layer (170) to protect the oxide layer (170) during later processing. The nitride layer (172) and oxide layer (170) are then patterned and etched to form a storage plate cavity (180). The capacitor array (182) is then formed in the storage plate cavity (180). The capacitor array (182) has a height approximately equal to the sum of said first and second thicknesses, so that the surface of the top node of the capacitor array (182) is co-planar with the upper surface of the surrounding oxide/nitride stack (170/172). Thus, the step height normally present between the capacitor array (182) and the peripheral area is avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.