Flash memory with improved erasability and its circuitry
US5770963A · kind A · utility
14Cited by
13References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 8, 1995 |
| Grant date | Jun 23, 1998 |
| Priority date | — |
| Expiry date | May 8, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory performs channel erasing or source erasing by applying a negative voltage to a control gate. The device includes a voltage restriction device which restricts the negative voltage to be applied to the control gate so that the negative voltage will be a constant value relative to the voltage of the channel or source. Alternatively, two voltage restricting devices restrict the negative voltage applied to the control gate and the voltage to be applied to the source so that the voltages will be a constant value relative to a common reference voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.