Low latency error reporting for high performance bus
US5771247A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Mar 4, 1996 |
| Grant date | Jun 23, 1998 |
| Priority date | — |
| Expiry date | Mar 4, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method are provided that use a determination of bad data parity and the state of an error signal (Derr.sub.--) as a functional signal indicating a specific type of error in a particular system component. If the Derr.sub.-- signal is active, the parity error recognized by the CPU was caused by a correctable condition in a data providing device. In this instance, the processor will read the corrected data from a buffer without reissuing a fetch request. When the CPU finds a parity error, but Derr.sub.-- is not active a more serious fault condition is identified (bus error or uncorrectable multibit error) requiring a machine level interrupt, or the like. And, when no parity is found by the CPU and Derr.sub.-- is not active, then the data is known to be valid and the parity/ECC latency is eliminated, thereby saving processing cycle time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.