Condensed microaddress generation in a complex instruction set computer
US5771365A · kind A · utility
12Cited by
2References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 1, 1995 |
| Grant date | Jun 23, 1998 |
| Priority date | — |
| Expiry date | Mar 1, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microarchitecture in a complex instruction computer system is disclosed employing a sparse microROM array and concatenation address circuitry for forming microaddress entry points, avoiding the need for a programmable logic array to translate instruction opcodes and avoiding duplicative entry points, thus minimizing the microROM array size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.