Method of making an SOI integrated circuit with ESD protection

US5773326A · kind A · utility

Assignee

• Motorola, Inc. · US

Inventors

• Percy V. Gilbert · Austin, US
• Paul G. Y. Tsui · Austin, US
• Stephen G. Jamison · Kyle, US
• James W. Miller · Austin, US

Key dates

• Filing date: Sep 19, 1996
• Grant date: Jun 30, 1998
• Expiry date: Sep 19, 2016

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/981

Abstract

An SOI structure (20) includes a semiconductor layer (15) formed on an insulating substrate (12). The semiconductor layer (15) is partitioned into an ESD protection portion (32) and a circuitry portion (34). A portion of the semiconductor layer (15) in the ESD protection portion (32) and a different portion of the semiconductor layer (15) in the circuitry portion (34) are differentially thinned. A device (60) which implements the desired circuit functions of the SOI structure (20) is fabricated in the circuitry portion (34). An ESD protection device (40) is fabricated in the ESD protection portion (32). The thick semiconductor layer (15) in the ESD protection portion (32) serves to distribute the ESD current and heat over a large area, thereby improving the ability of the SOI structure (20) to withstand an ESD event.