Percy V. Gilbert
10Patents
9h-index
25Co-inventors
68Inventor score
Filing activity: Jun 30, 1993 → Nov 4, 2005
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6362071B1 | Method for forming a semiconductor device with an opening in a dielectric layer | Electricity | 104 | Expired |
| US5885856A | Integrated circuit having a dummy structure and method of making | Electricity | 100 | Expired |
| US6991979B2 | Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs | Electricity | 46 | Expired |
| US5349224A | Integrable MOS and IGBT devices having trench gate structure | Electricity | 41 | Expired |
| US5708288A | Thin film silicon on insulator semiconductor integrated circuit with electrostatic damage protection and method | Electricity | 38 | Expired |
| US6806584B2 | Semiconductor device structure including multiple fets having different spacer widths | Emerging Cross-Sectional Technologies | 33 | Expired |
| US5744841A | Semiconductor device with ESD protection | Electricity | 25 | Expired |
| US5773326A | Method of making an SOI integrated circuit with ESD protection | Emerging Cross-Sectional Technologies | 20 | Expired |
| US5733794A | Process for forming a semiconductor device with ESD protection | Electricity | 14 | Expired |
| US7091128B2 | Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs | Electricity | 3 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.