Single transistor E.sup.2 PROM memory device
US5773861A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 1995 |
| Grant date | Jun 30, 1998 |
| Priority date | — |
| Expiry date | Nov 17, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/46
Abstract
A semiconductor memory cell device exhibiting superior cell reliability comprising a dual layer floating gate wherein the thin upper layer of the floating gate overlaps the edges of surrounding field insulating regions and has rounded edges to minimize leakage concerns. The tunnel dielectric separating the dual layer floating gate from the substrate comprises a layer of uniform thickness which is grown prior to the formation of the field insulating regions. The Fowler-Nordheim tunneling mechanism is used for programming and erasing the inventive cells in a programming process flow which comprises flash programming all cells on a word line, sensing current on a selected cell, and selectively erasing the charge on the cell by applying a higher voltage on the intersecting bit line than is applied to the word line, until the sensed current is as desired.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.