Floating gate FGPA cell with separated select device
US5773862A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 1996 |
| Grant date | Jun 30, 1998 |
| Priority date | — |
| Expiry date | Aug 27, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides for a programming portion of an FPGA cell of an integrated circuit and a process of manufacturing the programming portion. The programming portion has an EPROM transistor and a separated select transistor with the gate of the select transistor connected to the control gate of the EPROM transistor. Both transistors share a common N+ source/drain region, which is self-aligned with the gates of both transistors. With the select transistor separated from the EPROM transistor and the self-aligned common N+ region, the threshold voltage V.sub.T of the select transistor can be set precisely. This allows good control over the programming voltage for the control gate of the EPROM transistor and the time to program the floating gate of the EPROM transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.