Jack Peng
61Patents
22h-index
25Co-inventors
88Inventor score
Filing activity: Jun 6, 1995 → Jul 19, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6992925B2 | High density semiconductor memory cell and memory array using a single transistor and having counter-doped poly and buried diffusion wordline | Physics | 239 | Expired |
| US6667902B2 | Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric | Electricity | 123 | Expired |
| US5587945A | CMOS EEPROM cell with tunneling window in the read path | Physics | 98 | Expired |
| US6671040B2 | Programming methods and circuits for semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric | Electricity | 74 | Expired |
| US6777757B2 | High density semiconductor memory cell and memory array using a single transistor | Physics | 73 | Expired |
| US6845151B2 | Picture/sound output equipment with caller identification and volume adjustment functions | Electricity | 68 | Expired |
| US6700151B2 | Reprogrammable non-volatile memory using a breakdown phenomena in an ultra-thin dielectric | Electricity | 68 | Expired |
| US6972986B2 | Combination field programmable gate array allowing dynamic reprogrammability and non-votatile programmability based upon transistor gate oxide breakdown | Electricity | 67 | Expired |
| US6940751B2 | High density semiconductor memory cell and memory array using a single transistor and having variable gate oxide breakdown | Physics | 60 | Expired |
| US7269047B1 | Memory transistor gate oxide stress release and improved reliability | Physics | 60 | Expired |
| US6650143B1 | Field programmable gate array based upon transistor gate oxide breakdown | Electricity | 55 | Expired |
| US6822888B2 | Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric | Electricity | 51 | Expired |
| US6898116B2 | High density semiconductor memory cell and memory array using a single transistor having a buried N+ connection | Physics | 48 | Expired |
| US6798693B2 | Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric | Electricity | 46 | Expired |
| US7064973B2 | Combination field programmable gate array allowing dynamic reprogrammability | Electricity | 45 | Expired |
| US6856540B2 | High density semiconductor memory cell and memory array using a single transistor | Physics | 37 | Expired |
| US6956258B2 | Reprogrammable non-volatile memory using a breakdown phenomena in an ultra-thin dielectric | Electricity | 35 | Expired |
| US6791891B1 | Method of testing the thin oxide of a semiconductor memory cell that uses breakdown voltage | Physics | 33 | Expired |
| US6252273A | Nonvolatile reprogrammable interconnect cell with FN tunneling device for programming and erase | Electricity | 26 | Expired |
| US7471541B2 | Memory transistor gate oxide stress release and improved reliability | Physics | 26 | Active |
| US7031209B2 | Methods and circuits for testing programmability of a semiconductor memory cell and memory array using a breakdown phenomenon in an ultra-thin dielectric | Physics | 26 | Expired |
| US6766960B2 | Smart card having memory using a breakdown phenomena in an ultra-thin dielectric | Electricity | 25 | Expired |
| US5838040A | Nonvolatile reprogrammable interconnect cell with FN tunneling in sense | Electricity | 22 | Expired |
| US6526151B1 | High stability loudspeaker | Electricity | 21 | Expired |
| US5851886A | Method of large angle tilt implant of channel region | Electricity | 19 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.