Flash memory with row redundancy
US5774396A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 1996 |
| Grant date | Jun 30, 1998 |
| Priority date | — |
| Expiry date | Dec 9, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a flash memory with row redundancy. The memory includes an input terminal to receive an address and a command signal. A plurality of flash memory arrays are arranged as blocks, where each block includes a plurality of transistors organized in rows and columns and having respective wordlines, bitlines and a sourceline. A wordline decoder is coupled to the input terminal and a portion of the plurality of blocks and configured to decode a portion of the address and to receive a control signal to selectively apply a predetermined voltage to a wordline. A bitline decoder is coupled to the input terminal and to the plurality of blocks and configured to decode a portion of the address and to selectively pass a predetermined bitline to an output terminal. A match circuit is coupled to the input terminal and to a portion of the plurality of blocks and configured to decode a portion of the address and to receive the control signal to selectively apply a predetermined voltage to a wordline. A control circuit is coupled to the wordline decoder and the match circuit and configured to selectively activate one of the wordline decoder and the match circuit by the control sig…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.