Structure and method to prevent over erasure of nonvolatile memory transistors
US5774400A · kind A · utility
46Cited by
3References
33Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1996 |
| Grant date | Jun 30, 1998 |
| Priority date | — |
| Expiry date | Dec 23, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3468
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and structure for preventing over erasure in non-volatile memory cells uses simultaneous erase and program current injections which offset one another. These currents come from two separate injection points within the non-volatile memory transistor and are dominant at different points during the erase operation. The first occurring current erases the non-volatile device and the second prevents over erasure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.