Interfacing direct memory access devices to a non-ISA bus
US5774680A · kind A · utility
23Cited by
1References
65Claims
0Family size
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Key dates
| Filing date | Dec 11, 1995 |
| Grant date | Jun 30, 1998 |
| Priority date | — |
| Expiry date | Dec 11, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system having separate, yet compatible DMA controllers on a bus. Each DMA controller for controlling at least one DMA channel, each DMA controller having an independent set of registers for performing DMA operations and a configuration register for indicating channel status and designation. A DMA master for compatibly communicating with a processor and for initializing and communicating with the multiple DMA controllers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.