Serial interface speech synthesizers
US5774853A · kind A · utility
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5Claims
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Key dates
| Filing date | Jun 16, 1997 |
| Grant date | Jun 30, 1998 |
| Priority date | — |
| Expiry date | Jun 16, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG10L13/047
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Speech synthesizer systems avoid the need for a multi-path address bus coupling to a CPU by provision of serial interfaces requiring a total of only two or three signal paths to a CPU. By use of a counter circuit or shift register working in cooperation with a modified trigger signal circuit, a serially encoded control signal is internally converted to binary type signals which are coupled via an internal address bus to a speech synthesis unit for production of selected speech segment output signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.