Manufacturing method of semiconductor device
US5776812A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 1995 |
| Grant date | Jul 7, 1998 |
| Priority date | — |
| Expiry date | Mar 30, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
Abstract
A manufacturing method of a MOSFET having a channel part on the side surface of a groove, which does not permit the introduction of defects or contaminant into the channel part and which can make the shape of the groove uniform. An n.sup.- -type epitaxial layer having a low impurity concentration is formed on a main surface of an n.sup.+ -type semiconductor substrate. This surface is specified as a main surface, and chemical dry etching is applied to a specified region of this main surface. A region including a surface generated by the chemical dry etching is selectively oxidized to form a selective oxide film to a specified thickness. Following this process, p-type and n-type impurities are doubly diffused from the main surface to define the length of the channel and form a base layer and a source layer. Furthermore, the n.sup.+ -type semiconductor substrate is specified as a drain layer. After the double diffusion, a gate electrode is formed through a gate oxide film and a source electrode and a drain electrode are formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.