Process to manufacture a vertical gate-enhanced bipolar transistor
US5776813A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 1997 |
| Grant date | Jul 7, 1998 |
| Priority date | — |
| Expiry date | Oct 6, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/121
Abstract
A process for manufacturing a vertical gate-enhanced bipolar transistor is described. The process does not require the presence of an insulating substrate to electrically isolate devices and is suitable for both NPN as well as PNP bipolar transistors. The process begins with the formation of a buried layer. This layer is accessed from the surface through a suitable well region. Then a trench, shaped as a hollow square is formed, lined with a layer of gate oxide and then filled with low resistivity polysilicon to form the gate. A polysilicon emitter layer is formed in the interior of the square, following implantation of arsenic ions with thermal drive-in to form an emitter junction just below the surface. After formation of the emitter junction, isolation layers, including self-aligned spacers, are constructed to cover the polysilicon emitter layer. Another layer of polysilicon is then laid down and then boron ions are implanted. This is followed by a thermal drive-in to form a base contact. The polysilicon is then patterned and etched to serve as the base electrode. A layer of oxide is laid down and flowed to provide planarization/insulation and contact holes are etched in it. Fin…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.