Solid state imager having high frequency transfer mode
US5777671A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jan 17, 1996 |
| Grant date | Jul 7, 1998 |
| Priority date | — |
| Expiry date | Jan 17, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/73
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A control circuit generates a control signal which is of a low level during a certain period of time after the power supply of a solid state imager has been turned on or a power save mode thereof has been canceled, and of a high level after elapse of the period of time. Based on the control signal, a timing generator generates transfer clock signals having a high frequency than when the solid state imager is in a normal transfer mode, and applies the transfer clock signals to a CCD shift register to remove or transfer excessive invalid charges at a high rate therefrom. After the power supply has been turned on or the power save mode has been canceled, therefore, the time required to bring the solid state imager into a condition capable of imaging a subject is shortened.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.