High-speed dominant mode bus for differential signals
US5778204A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 1997 |
| Grant date | Jul 7, 1998 |
| Priority date | — |
| Expiry date | Jun 23, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/40052
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A bus circuit for implementing a high speed dominant logic bus for a differential signal. The bus circuit is useful in a communication network having a plurality of multi-port nodes that are coupled by point-to-point links that communicate differential signals. Each port in the node includes a bus driver that receives the differential signal received at the port. The bus driver supplies a differential current signal to a first bus. A terminator circuit is coupled to the first differential bus, to receive the differential current signals supplied from the ports. The terminator circuit, responsive to the differential current signal, outputs a differential voltage signal indicative of either a dominant state or a non-dominant state to a second differential bus, which is coupled to the plurality of ports for transmission. A biasing circuit for the bus drivers allows operation at low voltages, and furthermore insures the zero crossing of the differential voltage signal on the second differential bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.