Multiprocessing interrupt controller on I/O bus
US5778236A · kind A · utility
16Cited by
17References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 17, 1996 |
| Grant date | Jul 7, 1998 |
| Priority date | — |
| Expiry date | May 17, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessing computer system which includes an interrupt controller coupled to an expansion bus. The programmable interrupt controller has multiple storage locations at the same address for multiple CPUs. The CPUs are coupled to a host bus which in turn is coupled to the expansion bus by means of a bus bridge. An arbiter is coupled to the host bus for arbitrating bus mastership amongst the CPUs. CPU host owner identification for access to the storage locations is transferred across bus bridge to the programmable interrupt controller synchronized with the buffered address and data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.