bonded wafer processing
US5780311A · kind A · utility
44Cited by
7References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 15, 1997 |
| Grant date | Jul 14, 1998 |
| Priority date | — |
| Expiry date | Jan 15, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/938
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Warpage in a bonded wafer is limited by maintenance of a stress compensation layer on the backside of the bonded wafer during device fabrication processing. One embodiment applies a sacrificial polysilicon layer over a stress compensation silicon dioxide layer for bonded silicon wafers. The fabrication processing consumes the polysilicon layer but not the stress compensation silicon dioxide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.