Method of manufacturing a vertical semiconductor device
US5780324A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 1996 |
| Grant date | Jul 14, 1998 |
| Priority date | — |
| Expiry date | Feb 22, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
Abstract
A manufacturing method of a vertical DMOSFET having a concave channel structure, which does not permit the introduction of defects or contaminant into the channel part and which can make the shape of the groove uniform, is disclosed. On a surface of a (100)-oriented n.sup.- -on-n.sup.+ epitaxial wafer is formed an initial groove by chemical dry etching. The grooved surface is then oxidized by LOCOS technique to form a LOCOS oxide film, whereby the concave structure is formed on the epitaxial wafer. The concave width is set to be at least twice the concave depth, and the sidewall angle is set to be approximately 50.degree. to make the sidewall plane (111) of high channel mobility plane. Following this process, p-type and n-type impurities are diffused from the main surface using the LOCOS oxide film as a double diffusion mask to form a body region and a source region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.