Method of fabricating capacitor of semiconductor memory device
US5780334A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 1996 |
| Grant date | Jul 14, 1998 |
| Priority date | — |
| Expiry date | Oct 11, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/318
Abstract
A method of fabricating a capacitor of a semiconductor memory device includes the steps of: forming an interlevel insulating layer on a semiconductor substrate on which the capacitor will be formed, selectively etching a portion of the interlevel insulating layer placed on a capacitor forming portion to form a capacitor node hole, and forming a first temporary layer on the interlevel insulating layer, including a portion of the interlevel insulating layer in which the capacitor node hole is formed; forming a contact hole beneath the capacitor node hole in a capacitor contact portion; forming a conductive layer on the first temporary layer to bury the contact hole and the capacitor node hole, and then forming a second temporary layer on the conductive layer; etching back the second temporary layer through anisotropic etching process to expose the conductive layer, and to simultaneously form a temporary pillar layer inside the capacitor node hole, the temporary pillar layer being substantially surrounded by the conductive layer; removing a portion of the conductive layer placed on a portion other than the capacitor forming portion, to form a first capacitor electrode and to expose at…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.