Method for testing an electronic circuit by logically combining clock signals, and an electronic circuit provided with facilities for such testing
US5781025A · kind A · utility
3Cited by
8References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 2, 1996 |
| Grant date | Jul 14, 1998 |
| Priority date | — |
| Expiry date | Jul 2, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/30
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An electronic circuit has a plurality of nodes at which a plurality of clock signals are present in operational use. The clock signals should have a pre-determined timing relationship amongst themselves. The circuit includes logic circuitry having inputs connected to the nodes and having an output to provide a pulse train. Any discrepancy between the actual and ideal pulse trains indicates a fault.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.