Bit map addressing schemes for flash/memory
US5781472A · kind A · utility
19Cited by
35References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 2, 1997 |
| Grant date | Jul 14, 1998 |
| Priority date | — |
| Expiry date | May 2, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Sense path and write path architectures for read and write accesses of a memory device having memory cells that store n binary bits are disclosed. "By-output" architectures provide one output per bit such that each selected memory cell is mapped to n outputs and the n bits stored in the selected memory cell are read in parallel. "By-address" architectures provide one address per bit such that each selected memory cell is mapped to one output, and the n bits stored in the selected memory cell are read sequentially.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.