Main memory arbitration with priority scheduling capability including multiple priorty signal connections
US5781927A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 1996 |
| Grant date | Jul 14, 1998 |
| Priority date | — |
| Expiry date | Jan 30, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A main memory arbitration arrangement for a computer system. It features the ability to set priorities between a main system and peripheral system to optimize system efficiency. The arbitration arrangement comprises a main memory controller and a peripheral system. The main memory controller has ports for issuing memory request signals of various priority levels determined based on urgency of the need for the main memory. The main memory controller will determine whether to yield the control of the main memory to the peripheral system based on the priority level of the memory request signal received and the urgency of the current operating condition of the main system. The result is the enhancing of the overall efficiency of the computer system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.