Structure and method for manufacturing improved FETs having T-shaped gates
US5783479A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 1997 |
| Grant date | Jul 21, 1998 |
| Priority date | — |
| Expiry date | Jun 23, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure and method for manufacturing improved FETs having T-shaped gates can reduce the parasitic resistance of the gate and source/drain of an FET. In the improved FETs having T-shaped gates formed according to the invention, since a buffer layer under spacers comprises a gate oxide layer and a thicker first dielectric layer, there is no stress problem as in the prior art. Furthermore, since the polysilicon gate is lower in height than the spacers, a bridge effect can be prevented. Meanwhile, since a T-shaped conductive layer is formed to increase the equivalent width of the gate, thereby avoiding the narrow line-width effect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.