Two-device memory cell on SOI for merged logic and memory applications
US5784311A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 1997 |
| Grant date | Jul 21, 1998 |
| Priority date | — |
| Expiry date | Jun 13, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A two-MOSFET device memory cell, based on conventional SOI complementary metal oxide technology, in which charge is stored on the body of a first MOSFET, with a second MOSFET connected to the body for controlling the charge in accordance with an information bit. Depending on the stored charge, the body of the first MOSFET is in depletion or non-depletion condition. A reference voltage connected to the gate of the first MOSFET causes a bipolar current flow in response to a pulsed voltage on the first MOSFET's source when the MOSFET is in a non-depletion condition, due to a temporary forward bias of the source to body junction. The bipolar current substantially adds to the field-effect current, thereby multiplying the effective charge read from the first MOSFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.