Inventor · Pound Ridge, NY, US

Ghavam G. Shahidi

377Patents
25h-index
170Co-inventors
93Inventor score

Filing activity: Jul 19, 1993 → Sep 29, 2021

Most-cited inventions

PatentTitleAreaCited byStatus
US8906755B1 Active matrix using hybrid integrated circuit and bipolar transistor Electricity 273 Active
US5784311A Two-device memory cell on SOI for merged logic and memory applications Electricity 215 Expired
US6333532A Patterned SOI regions in semiconductor chips Emerging Cross-Sectional Technologies 183 Expired
US6566177B1 Silicon-on-insulator vertical array device trench capacitor DRAM Electricity 181 Expired
US6214694A Process of making densely patterned silicon-on-insulator (SOI) region on a wafer Electricity 149 Expired
US7002214B1 Ultra-thin body super-steep retrograde well (SSRW) FET devices Electricity 140 Expired
US6432754B1 Double SOI device with recess etch and epitaxy Electricity 122 Expired
US5811857A Silicon-on-insulator body-coupled gated diode for electrostatic discharge (ESD) and analog applications Electricity 102 Expired
US7968459B2 Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors Emerging Cross-Sectional Technologies 102 Active
US6653698B2 Integration of dual workfunction metal gate CMOS devices Electricity 98 Expired
US8169025B2 Strained CMOS device, circuit and method of fabrication Electricity 57 Active
US6180486A Process of fabricating planar and densely patterned silicon-on-insulator structure Electricity 52 Expired
US6131182A Method and apparatus for synthesizing and optimizing control logic based on SRCMOS logic array macros Physics 51 Expired
US6426252B1 Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap Electricity 49 Expired
US8912020B2 Integrating active matrix inorganic light emitting diodes for display devices Electricity 46 Active
US5298786A SOI lateral bipolar transistor with edge-strapped base contact and method of fabricating same Electricity 35 Expired
US9093533B2 FinFET structures having silicon germanium and silicon channels Electricity 31 Active
US8822320B2 Dense finFET SRAM Electricity 30 Active
US8169024B2 Method of forming extremely thin semiconductor on insulator (ETSOI) device without ion implantation Electricity 30 Active
US6800518B2 Formation of patterned silicon-on-insulator (SOI)/silicon-on-nothing (SON) composite structure by porous Si engineering Electricity 28 Expired
US7855455B2 Lock and key through-via method for wafer level 3 D integration and structures produced Electricity 28 Active
US6521947B1 Method of integrating substrate contact on SOI wafers with STI process Electricity 27 Expired
US8207038B2 Stressed Fin-FET devices with low contact resistance Electricity 26 Active
US9064722B2 Breakdown voltage multiplying integration scheme Electricity 26 Active
US7365378B2 MOSFET structure with ultra-low K spacer Electricity 25 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.