Method of manufacturing a semiconductor package
US5786239A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 1996 |
| Grant date | Jul 28, 1998 |
| Priority date | — |
| Expiry date | Sep 20, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/3473
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to a method of manufacturing a semiconductor package of the present invention, a plurality of leads and a large number of minute convex portions are respectively formed by plating on a surface of a metal base and in an outer peripheral area of the leads thereon. An insulative film for holding each of the leads is formed. A solder resist film is formed selectively on a portion including the outer peripheral area having the minute convex portions thereon. A projecting electrode is formed on an outer lead portion of each of the leads through an opening of the solder resist film on an outer lead portion of each of the leads. The metal base is selectively removed except a joint portion thereof on an outer periphery to separate the respective leads. Inner lead portions of the leads and a semiconductor chip are jointed together. The joint portion of the metal base is cut off.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.