Methods of forming integrated semiconductor devices having improved channel-stop regions therein, and devices formed thereby
US5786265A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 1996 |
| Grant date | Jul 28, 1998 |
| Priority date | — |
| Expiry date | May 9, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76216
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming semiconductor devices containing field oxide and channel-stop isolation regions therein include the steps of forming a plurality of first channel-stop isolation regions by implanting first conductivity type impurities at a first dose level into a face of a semiconductor substrate and then forming respective field oxide isolation regions at the locations where the first channel-stop isolation regions have been implanted. A conductive layer, which contacts active regions of the substrate and covers the field oxide isolation regions, is then patterned over the field oxide isolation regions to expose central portions of the upper surfaces of the field oxide isolation regions. The patterned conductive layer constitutes a landing pad layer which is preferably used as a mask during the formation of second channel-stop isolation regions in the substrate, by implanting first conductivity type impurities through the exposed upper surfaces of the field oxide isolation regions, into the centers of the first channel-stop isolation regions. During this step, the impurities are implanted at a higher dose and energy level so that the first and second channel-stop regions collect…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.