System and method for improving a random access memory (RAM)
US5787041A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1996 |
| Grant date | Jul 28, 1998 |
| Priority date | — |
| Expiry date | Oct 1, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1042
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved random access memory (RAM) system enhances the speed and reduces power dissipation and logic complexity associated with a RAM. The RAM system includes first and second pluralities of RAM cell columns. Each of the columns includes (1) at least one RAM cell, each RAM cell configured to read and write a respective logic state and (2) bit and nbit connections (differential and complimentary) connected to each of the RAM cells. A first multiplexer is designed to multiplex the bit and nbit connections of the first plurality of RAM cell columns. A second multiplexer is configured to multiplex the bit and nbit connections of the second plurality of columns. Decode logic controls the first and second multiplexers, and the decode logic accesses a particular column and cell in one of the first and second pluralities during each memory access. A sense amplifier is configured to read the bit and nbit connections of the first and second pluralities via respectively the first and second multiplexers. The sense amplifier is designed to output a logic state from any of the cells based upon a voltage differential and a polarity between the bit and nbit connections of any of the columns. …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.