Circuit and method for testing an integrated circuit
US5787096A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 1996 |
| Grant date | Jul 28, 1998 |
| Priority date | — |
| Expiry date | Apr 23, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/46
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A selector circuit (12) for placing a memory device (10) in test mode. The selector circuit (12) uses a logic circuit (26) to determine when a control signal provided to a pin of the memory device (10) maintains a first logic level for a period of time exceeding the specification for the control signal in normal operation. A multiplexer (24) receives the control signal and a substitute control signal at an alternate pin of the memory device. The substitute control signal is used in place of the control signal during the test. The output of the logic circuit (26) is coupled to control the multiplexer (24) to select the control signal for use in addressing a cell of the memory device (10) in normal operation and to select the substitute control signal for use in addressing a cell of the memory device (10) in test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.