Method of adding on chip capacitors to an integrated circuit
US5789303A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 1996 |
| Grant date | Aug 4, 1998 |
| Priority date | — |
| Expiry date | Jul 11, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A capacitor structure and method of forming a capacitor structure for an integrated circuit is provided. The capacitor structure, comprising a bottom electrode, capacitor dielectric and top electrode, is formed on a passivation layer overlying the interconnect metallization. The capacitor electrodes are interconnected to the underlying integrated circuit from underneath, through conductive vias, to the underlying interconnect metallization. The method provides for adding capacitors to an otherwise completed and passivated integrated circuit. The structure is particularly applicable for ferroelectric capacitors. The passivation layer acts as a barrier layer for a ferroelectric dielectric. Large area on-chip capacitors may added without affecting the interconnect routing or packing density of the underlying devices, and may be added almost independently of the process technology used formation of the underlying integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.