Single poly memory cell and array
US5789776A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 1996 |
| Grant date | Aug 4, 1998 |
| Priority date | — |
| Expiry date | Sep 18, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A non-volatile memory cell array using only a single level of polysilicon and a single level of metal has programmable single transistor memory cells on a semiconductor substrate of a first conductivity type, a well of a second conductivity type in the substrate, parallel bitlines oriented in a first direction, and reference line segments oriented in the first direction. Each reference line is paired with one of each bitline. The array also has parallel word lines oriented in a second direction to form an array of intersections with the pairs of bitline/reference line pairs, and a rewriteable single transistor memory cell at each intersection point.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.