Bare die multiple dies for direct attach
US5790384A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 1997 |
| Grant date | Aug 4, 1998 |
| Priority date | — |
| Expiry date | Jun 26, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package includes a substrate formed from a first die and its attendant wiring interconnections, having a first thermal coefficient of expansion. The first die includes primary input/output (I/O) interconnections for the chip package. Also provided is a second die that includes escape wiring formed on that die and coupled to the primary I/O interconnections through the first die. The second die has a second thermal coefficient of expansion similar to the first thermal coefficient of expansion. The chip package also includes connectors that couple the primary I/O interconnections of the first die to a second level package. An interposer may be provided to couple the primary I/O interconnections to the second level package. The second die is smaller than the first die. The peripheral area of the first die is left exposed when the second die is coupled to the first die so that sufficient I/O interconnections may be formed for the primary I/O interconnections on the first die. The second die provides and receives signals which may include the second die's primary I/O to and from the first die. Wiring may be shared between the first die and the second die in a manner optimal for d…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.