Register file with bypass capability
US5790461A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 1, 1997 |
| Grant date | Aug 4, 1998 |
| Priority date | — |
| Expiry date | Aug 1, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Control circuitry for a register file is provided which allows immediate or rapid output of input write data by bypassing the need to store the data and then read it out of the register file. In each pairing of memory cells, the read line is coupled to both the storage cell and to the write line. The connection to the write line is configured so that, when the connection is activated, such as by turning on a transistor, the magnitude of the data signal provided from the write line to the read line is large enough to overpower whatever signal is being output to the read line from the memory cell. In this way, when the connection from the write line to the read line is activated, the write line will output the information on the read line, rather than the information in the storage cell. The information on the read line can then be output onto the write line without the information first being stored in the memory cell. This is advantageous when the write data is available at a time when its validity is unknown. Preferably, the device is further configured to permit writing of the data from the write line into the memory cell once the validity of the data is ascertained, e.g., under …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.