Configurable digital wireless and wired communications system architecture for implementing baseband functionality
US5790817A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 1996 |
| Grant date | Aug 4, 1998 |
| Priority date | — |
| Expiry date | Sep 25, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A configurable multiprocessor communications architecture which performs digital communications functions and which is configurable for different digital communications standards, such as various digital cellular standards. In the preferred embodiment, the multiprocessor architecture includes two or more digital signal processing cores, a microcontroller or micro-scheduler, a voice coder/decoder (codec), and a relatively low performance central processing unit (CPU). Each of the above devices are coupled to a system memory. The general purpose CPU preferably performs user interface functions and overall communications management functions. A CPU local memory and various peripheral devices are coupled through a CPU local bus to the CPU, and these devices are accessible to the CPU without the CPU having to access the main system bus. A dual port bus arbiter is preferably coupled between the CPU and the system bus and controls access to the system bus and the CPU local bus. The micro-scheduler operates to schedule operations and/or functions, as well as dynamically control the clock rates, of each of the DSPs and the hardware acceleration logic to achieve the desired throughput while …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.