Method and apparatus for providing a re-ordered instruction cache in a pipelined microprocessor
US5790822A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 1996 |
| Grant date | Aug 4, 1998 |
| Priority date | — |
| Expiry date | Mar 21, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3853
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for executing instructions in a pipelined microprocessor. The method includes re-ordering the set of instructions prior to loading the instructions into an instruction cache. In one embodiment, a re-ordering unit receives the set of instructions as a trace segment made of a set of basic blocks of instructions in a logical order of execution. After being re-ordered, the instructions are presented to the reordered instruction cache in bundles. When an instruction is unavailable, possibly due to an unresolved data dependency, no operation codes (nops) are inserted into the bundle in place of an in place of an instruction, creating fixed length bundles. In a second embodiment, nops are not used. Variable length bundles are produced by using an additional bit(s) per instruction to mark the end of the bundles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.