Synchronizing unit having two registers serially connected to one clocked elements and a latch unit for alternately activating the registers in accordance to clock signals
US5790891A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 1996 |
| Grant date | Aug 4, 1998 |
| Priority date | — |
| Expiry date | Jan 11, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data transfer synchronizing unit is provided for generating flags indicating the fullness state of a data transfer element. The determining unit includes the first and second counters operating according to first and second clock signals, first and second registers, serially connected to the output of the second counter, a latch unit and a comparator. The first register is clocked by the second clock signal and the second register is clocked by the first clock signal. The latch unit alternately activates the first and second registers to receive data in accordance with the second and first clock signals, respectively. The comparator produces the flags by comparing the output of the first counter with the output of the second register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.