Method of forming a low cost DRAM cell with self aligned twin tub CMOS devices and a pillar shaped capacitor
US5792680A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 1996 |
| Grant date | Aug 11, 1998 |
| Priority date | — |
| Expiry date | Nov 25, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/318
Abstract
The invention is a method of forming a reduced cost DRAM. The process has two embodiments for forming twin wells and two embodiments for forming pillar shaped capacitor electrodes. The twin well embodiments are simple low cost processes. The embodiments for forming the electrode pillars begin by forming a tungsten silicide conductive layer on a first planarization layer. For the first embodiment, the pillars are formed using a photolithography mask with a pattern of spaced transparent areas. The dimensions of the spaced transparent areas and distances between the spaced transparent areas are smaller that the resolution of the lithographic tool. Spaced oxide islands are formed with the mask and are used as an etch mask to form spaced pillars from the conductive layer. This first embodiment for fabricating the multiple pillar capacitor forms pillars of a smaller dimension than the resolution of the photolithography tool. The second embodiment for forming the pillars involves using small titanium silicide islands as an etch mask to define the pillars.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.